Cover
Vol. 16 No. 2 (2025)

Published: December 15, 2025

Pages: 117-128

Review Paper

Challenges and Prospects of Nanoscale MOSFET Scaling: A Review

Ahmed S. Al-Jawadi 1 Mohammad Tariq Yaseen Qais Thanon Najim 2
1Department of Electrical Engineering, Collage of Engineering University of Mosul, Mosul, Iraq
2Department of Electronic Engineering, Collage of Electronics Ninevah university, Mosul, Iraq
History
  • Received: July 4, 2025
  • Revised: October 15, 2025
  • Accepted: November 18, 2025
  • Available Online: December 15, 2025
DOI

https://doi.org/10.37649/AJES-25-018

Abstract

The nonstop scaling of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is considered a driving force in semiconductor technology, allowing higher integration densities, enhanced performance, and reduced power consumption. However, fundamental challenges arise as device dimensions shrink to the nanoscale, such as short-channel effects, threshold voltage variation, leakage currents, and gate oxide tunneling. This study critically surveys these scaling limitations and shows potential solutions, such as high-k gate dielectrics, metal gate integration, and novel device architectures. Other transistor designs, including FinFETS, Gate-All-Around (GAA) transistors, and emerging beyond-CMOS devices, are assessed for their potential to extend Moore's Law. This study also addresses advancements in materials, including two-dimensional (2D) semiconductors and carbon-based nanostructures, that offer promising substitutes to conventional silicon technology. Regardless of these innovations, significant obstacles remain in achieving fabrication, reliability, and cost-effectiveness at sub-5nm nodes. This review paper provides insights into current progress and future guide for nanoscale MOSFET development, comprehensively assessing the challenges and opportunities in next-generation transistor technology. The findings aim to guide researchers and industry professionals toward sustainable semiconductor scaling approaches.

Keywords

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